LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 195
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
12.8.2 I
12.8.3 I
12.8.4 I
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
Each I
Status register is Read-Only.
Table 211. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 212. I
This register is readable and writable and are only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
Bit
2:0
7:3
31:8 -
Bit
7:0
31:8 -
2
2
2
2. The General Call address has been received while the General Call bit (GC) in I2ADR
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
C Status register (I2C0STAT - 0x4000 0004)
C Data register (I2C0DAT - 0x4000 0008)
C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
is set.
Symbol Description
Data
Symbol
-
Status
2
C Status register reflects the condition of the corresponding I
2
2
C Status register (I2C0STAT - 0x4000 0004) bit description
C Data register (I2C0DAT - 0x4000 0008) bit description
This register holds data values that have been received or are to
be transmitted.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
interface.
Reserved. The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
2
C states. When any of these states entered, the SI bit will
2
2
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
C is in the master receiver mode.
C is in the addressed slave receiver mode.
Chapter 12: LPC13xx I2C-bus controller
Table 228
2
2
C
C interface is set to
2
C interface. The I
UM10375
© NXP B.V. 2010. All rights reserved.
to
Reset value
0
-
Table
0
Reset value
0x1F
-
197 of 333
231.
2
C
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