LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 222
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
Table 232. Miscellaneous States
UM10375
User manual
Status
Code
(I2CSTAT)
0xF8
0x00
12.11.6.1 Simultaneous Repeated START conditions from two masters
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
12.11.6 Some special cases
2
causes the I
clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see
either master since they were both transmitting the same data.
If the I
a Repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
C block
•
•
•
•
•
2
C-bus
Simultaneous Repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I
I
Bus error
2
2
C-bus obstructed by a LOW level on SCL or SDA
C hardware has facilities to handle the following special cases that may occur
2
C hardware detects a Repeated START condition on the I
Application software response
To/From I2DAT
No I2DAT action
No I2DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
2
C-bus
To I2CON
STA STO SI
0
No I2CON action
Figure
1
0
34). Until this occurs, arbitration is not lost by
AA
X
Chapter 12: LPC13xx I2C-bus controller
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
2
C-bus before generating
UM10375
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
224 of 333
C block
2
C
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