LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 319

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Table 107. IOCON_PIO2_5 register (IOCON_PIO2_5,
Table 108. IOCON_PIO3_5 register (IOCON_PIO3_5,
Table 109. IOCON_PIO0_6 register (IOCON_PIO0_6,
Table 110. IOCON_PIO0_7 register (IOCON_PIO0_7,
Table 111. IOCON_PIO2_9 register (IOCON_PIO2_9,
Table 112. IOCON_PIO2_10 register (IOCON_PIO2_10,
Table 113. IOCON_PIO2_2 register (IOCON_PIO2_2,
Table 114. IOCON_PIO0_8 register (IOCON_PIO0_8,
Table 115. IOCON_PIO0_9 register (IOCON_PIO0_9,
Table 116. IOCON_SWCLK_PIO0_10 register
Table 117. IOCON_PIO1_10 register (IOCON_PIO1_10,
Table 118. IOCON_PIO2_11 register (IOCON_PIO2_11,
Table 119. IOCON_R_PIO0_11 register
Table 120. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0,
Table 121. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1,
Table 122. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2,
Table 123. IOCON_PIO3_0 register (IOCON_PIO3_0,
Table 124. IOCON_PIO3_1 register (IOCON_PIO3_1,
Table 125. IOCON_PIO2_3 register (IOCON_PIO2_3,
Table 126. IOCON_SWDIO_PIO1_3 register
Table 127. IOCON_PIO1_4 register (IOCON_PIO1_4,
Table 128. IOCON_PIO1_11 register (IOCON_PIO1_11,
Table 129. IOCON_PIO3_2 register (IOCON_PIO3_2,
Table 130. IOCON_PIO1_5 register (IOCON_PIO1_5,
Table 131. IOCON_PIO1_6 register (IOCON_PIO1_6,
Table 132. IOCON_PIO1_7 register (IOCON_PIO1_7,
Table 133. IOCON_PIO3_3 register (IOCON_PIO3_3,
Table 134. IOCON SCK location register (IOCON_SCKLOC,
UM10375
User manual
address 0x4004 4044) bit description . . . . . . .90
address 0x4004 4048) bit description . . . . . . .91
address 0x4004 404C) bit description . . . . . . .91
address 0x4004 4050) bit description. . . . . . . .92
address 0x4004 4054) bit description . . . . . . .92
address 0x4004 4058) bit description . . . . . . .93
address 0x4004 405C) bit description . . . . . . .93
address 0x4004 4060) bit description . . . . . . .94
address 0x4004 4064) bit description . . . . . . .94
(IOCON_SWCLK_PIO0_10, address 0x4004
4068) bit description . . . . . . . . . . . . . . . . . . . .95
address 0x4004 406C) bit description . . . . . . .96
address 0x4004 4070) bit description . . . . . . .96
(IOCON_R_PIO0_11, address 0x4004 4074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
address 0x4004 4078) bit description . . . . . . .98
address 0x4004 407C) bit description . . . . . . .99
address 0x4004 4080) bit description . . . . . .100
address 0x4004 4084) bit description . . . . . .100
address 0x4004 4088) bit description . . . . . .101
address 0x4004 408C) bit description . . . . . .101
(IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description . . . . . . . . . . . . . . . . . . . . . . . .102
address 0x4004 4094) bit description . . . . . .103
address 0x4004 4098) bit description . . . . . .104
address 0x4004 409C) bit description . . . . .104
address 0x4004 40A0) bit description . . . . . .105
address 0x4004 40A4) bit description . . . . . .105
address 0x4004 40A8) bit description . . . . . .106
address 0x4004 40AC) bit description . . . . . .106
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Table 135. LPC13xx pin configuration overview . . . . . . . 108
Table 136. LPC1313/43 LQFP48 pin description table . 113
Table 137. LPC1311/13/42/43 HVQFN33 pin description
Table 138. GPIO configuration . . . . . . . . . . . . . . . . . . . . 119
Table 139. GPIO pin description
Table 140. Register overview: GPIO (base address port 0:
Table 141. GPIOnDATA register (GPIO0DATA, address
Table 142. GPIOnDIR register (GPIO0DIR, address 0x5000
Table 143. GPIOnIS register (GPIO0IS, address 0x5000
Table 144. GPIOnIBE register (GPIO0IBE, address 0x5000
Table 145. GPIOnIEV register (GPIO0IEV, address 0x5000
Table 146. GPIOnIE register (GPIO0IE, address 0x5000
Table 147. GPIOnIRS register (GPIO0IRS, address 0x5000
Table 148. GPIOnMIS register (GPIO0MIS, address 0x5000
Table 149. GPIOnIC register (GPIO0IC, address 0x5000
Table 150. USB related acronyms, abbreviations, and
Table 151. Fixed endpoint configuration . . . . . . . . . . . . . 127
Table 152. USB device pin description . . . . . . . . . . . . . . 130
Table 153. USB device controller clock sources. . . . . . . 131
Table 154. Register overview: USB device (base address
Table 155. USB Device Interrupt registers bit allocation. 133
Table 156. USB Device Interrupt Status register
Table 157. USB Device Interrupt Enable register
Table 158. USB Device Interrupt Clear register
Table 159. USB Device Interrupt Set register (USBDevIntSet
Chapter 21: LPC13xx Supplementary information
address 0x4004 40B0) bit description . . . . . . 107
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002
0000; port 3: 0x5003 0000) . . . . . . . . . . . . . . 120
0x5000 3FFC; GPIO1DATA, address 0x5001
3FFC; GPIO2DATA, address 0x5002 3FFC;
GPIO3DATA, address 0x5003 3FFC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8000 to GPIO3DIR, address 0x5003 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8004 to GPIO3IS, address 0x5003 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8008 to GPIO3IBE, address 0x5003 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
800C to GPIO3IEV, address 0x5003 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8010 to GPIO3IE, address 0x5003 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8014 to GPIO3IRS, address 0x5003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8018 to GPIO3MIS, address 0x5003 8018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
801C to GPIO3IC, address 0x5003 801C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
definitions used in this chapter. . . . . . . . . . . . 126
0x4002 0000) . . . . . . . . . . . . . . . . . . . . . . . . 133
(USBDevIntSt - address 0x4002 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 134
(USBDevIntEn - address 0x4002 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
(USBDevIntClr - address 0x4002 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
- address 0x4002 000C) bit description . . . . . 135
[1]
. . . . . . . . . . . . . . . . . 119
UM10375
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