LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 202

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
12.9.3 Slave Receiver mode
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table
After a Repeated START condition, I
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, write any of the Slave Address registers (I2ADR0-3) and write
the I
Table 223. I2C0CONSET and I2C1CONSET used to configure Slave mode
I2EN must be set to 1 to enable the I
its own slave address or the General Call address. The STA, STO and SI bits are set to 0.
After I2ADR and I2CONSET are initialized, the I
its own address or general address followed by the data direction bit. If the direction bit is
0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
Bit
Symbol
Value
Fig 23. Format of Master Receiver mode
Fig 24. A Master Receiver switches to Master Transmitter after sending Repeated START
S
S
from Master to Slave
from Slave to Master
2
C Control Set register (I2CONSET) as shown in
229.
From master to slave
From slave to master
SLA
SLAVE ADDRESS
7
-
-
R
All information provided in this document is subject to legal disclaimers.
A
6
I2EN
1
DATA
Rev. 2 — 7 July 2010
n bytes data transmitted
RW=1
5
STA
0
A
2
2
A
DATA
C may switch to the master transmitter mode.
C function. AA bit must be set to 1 to acknowledge
4
STO
0
A
DATA
Chapter 12: LPC13xx I2C-bus controller
2
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr
C interface waits until it is addressed by
3
SI
0
Table
SLA
n bytes data received
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
SLA = Slave Address
Sr = Repeated START condition
A
223.
2
AA
1
W
DATA
A
UM10375
1
-
-
© NXP B.V. 2010. All rights reserved.
DATA
A
A
0
-
-
204 of 333
P
P