ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet

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ATMEGA16U2-MU

Manufacturer Part Number
ATMEGA16U2-MU
Description
MCU AVR 16K FLASH USB 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16U2-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Core
AVR8
Processor Series
ATMEGA16x
Data Bus Width
8 bit
Maximum Clock Frequency
16 MHz
Data Ram Size
1.25 KB
Data Rom Size
512 B
Number Of Programmable I/os
22
Number Of Timers
2
Mounting Style
SMD/SMT
Height
0.95 mm
Interface Type
SPI, UART
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
5 mm
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16U2-MU
Manufacturer:
RALINK
Quantity:
2 400
Features
Note:
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
Peripheral Features
On Chip Debug Interface (debugWIRE)
Special Microcontroller Features
I/O and Packages
Operating Voltages
Operating temperature
Maximum Frequency
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– 8K/16K/32K Bytes of In-System Self-Programmable Flash
– 512/512/1024 EEPROM
– 512/512/1024 Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
– Suspend/Resume Interrupts
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
– 22 Programmable I/O Lines
– QFN32 (5x5mm) / TQFP32 packages
– 2.7 - 5.5V
– Industrial (-40°C to +85°C)
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
PWM channels)
(three 8-bit PWM channels)
1. See
In-System Programming by on-chip Boot Program hardware-activated after
reset
True Read-While-Write Operation
IN or Out Directions
Bulk, Interrupt and IsochronousTransfers
Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer
“Data Retention” on page 6
®
8-Bit Microcontroller
for details.
(1)
8-bit
Microcontroller
with
8/16/32K Bytes
of ISP Flash
and USB
Controller
ATmega8U2
ATmega16U2
ATmega32U2
7799D–AVR–11/10

ATMEGA16U2-MU Summary of contents

Page 1

... Industrial (-40°C to +85°C) • Maximum Frequency – 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range Note: 1. See “Data Retention” on page 6 ® 8-Bit Microcontroller (1) for details. 8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller ATmega8U2 ATmega16U2 ATmega32U2 7799D–AVR–11/10 ...

Page 2

Pin Configurations Figure 1-1. Pinout XTAL1 2 (PC0) XTAL2 GND 3 VCC 4 QFN32 (PCINT11 / AIN2 ) PC2 5 (OC.0B / INT0) PD0 6 (AIN0 / INT1) PD1 7 (RXD1 / AIN1 / ...

Page 3

Overview The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 4

... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8U2/16U2/32U2 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8U2/16U2/32U2 are supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...

Page 5

Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C ...

Page 6

... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent ...

Page 7

AVR CPU Core 6.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

Page 8

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...

Page 9

Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact ...

Page 10

Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the ...

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Figure 6-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.6 Stack Pointer The Stack is mainly used for storing ...

Page 12

SPH and SPL – Stack Pointer High and Low Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by ...

Page 13

Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be ...

Page 14

CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char ...

Page 15

Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...

Page 16

AVR Memories This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. ...

Page 17

Figure 7-1. 7.2 SRAM Data Memory Figure 7-2 The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O ...

Page 18

The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter- nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing modes. The Register File is described in Figure 7-2. 7.2.1 Data Memory Access ...

Page 19

For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 7.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in ...

Page 20

Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ...

Page 21

EECR – The EEPROM Control Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM ...

Page 22

Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while ...

Page 23

Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: 7799D–AVR–11/10 (1) ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, ...

Page 24

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

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GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value 7799D–AVR–11/ MSB R/W R/W R/W R ATmega8U2/16U2/32U2 LSB R/W R/W R/W R ...

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System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 27

USB Clock – clk USB The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48 MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock ...

Page 28

Figure 8-3. USB non-Idle CPU Clock External Oscillator RC oscillator 8.2.2 Clock switch Algorythm 8.2.2.1 Swith from external clock to RC clock if (Usb_suspend_detected()) { } 8.2.2.2 Switch from RC clock to external clock if (Usb_wake_up_detected()) { } 7799D–AVR–11/10 Example ...

Page 29

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 8-1. ...

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The oscillator is required to oscillate for a minimum number of cycles before the clock is consid- ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock ...

Page 31

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 8-4. Table 8-4. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast ...

Page 32

Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. This Crystal Oscillator is ...

Page 33

Table 1. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising ...

Page 34

Notes: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-5 on page Table 8-7. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 7799D–AVR–11/10 1. The device is shipped ...

Page 35

External Clock The device can utilize a external clock source as shown in external clock, the CKSEL Fuses must be programmed as shown in Figure 8-5. When this clock source is selected, start-up times are determined by the SUT ...

Page 36

This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous ...

Page 37

Figure 8-6. XTAL1 XTAL2 8.11 Register Description 8.11.1 CLKSEL0 – Clock Selection Register 0 Bit (0xD0) Read/Write Initial Value • Bit 7:6 – RCSUT[1:0]: SUT for RC oscillator These 2 bits are the SUT value for the RC Oscillator. If ...

Page 38

The firmware has to check if the clock is correctly started before selected it. 8.11.2 CLKSEL1 – Clock Selection Register 1 Bit (0xD1) Read/Write Initial Value • Bit 7:4 – RCCKSEL[3:0]: CKSEL ...

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The oscillator can be calibrated to frequencies as specified page Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM ...

Page 40

Table 8-9. CLKPS3 8.11.6 PLLCSR – PLL Control and Status Register Bit 0x29 (0x49) Read/Write Initial Value • Bit 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero. • Bit 4 ...

Page 41

Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started. Note that the Calibrated 8 MHz Internal RC oscillator is automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) ...

Page 42

Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to ...

Page 43

Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk and clk CPU Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow, USART Transmit ...

Page 44

Waking up a module, which is done by clearing the bit in PRR, puts the module in the same ...

Page 45

V input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal ...

Page 46

PRR0 – Power Reduction Register 0 Bit (0x64) Read/Write Initial Value • Bit 7:6 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic ...

Page 47

System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...

Page 48

Figure 10-1. Reset Logic BODLEVEL [2..0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...

Page 49

Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...

Page 50

Brown-out Detection ATmega8U2/16U2/32U2 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. ...

Page 51

This allows the device to stay attached to the bus during and after the reset, while enhancing firmware reliability. Figure 10-7. USB Reset During Operation 10.3 Internal Voltage Reference ATmega8U2/16U2/32U2 features an internal bandgap reference. This reference ...

Page 52

The WDT gives an interrupt or a system reset when the counter reaches two times the given time-out value. In normal operation mode required that the system uses the WDR ...

Page 53

While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also includes a clock divider that directly acts on the clock source. This divider handles odd division factors (3, 5, 7). In combination with the ...

Page 54

Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. ...

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Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching ...

Page 56

Bit 5 – USBRF: USB Reset Flag This bit is set if a USB Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 4 – Res: Reserved ...

Page 57

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 10-1. WDTON (Fuse) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 0 (programmed) • Bit 4 ...

Page 58

Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is enabled. WDEWIF is automatically cleared by hardware when executing the corresponding ...

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Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1) (Continued) WDP3 WDP2 WDP1 WDP0 Table 10-4. Watchdog ...

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Table 10-5. Watchdog Timer Prescale Select, DIV = 2 (CLKwdt = CLK128 / 5) WDP3 WDP2 WDP1 WDP0 ...

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Table 10-6. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7) (Continued) WDP3 WDP2 WDP1 WDP0 Table 10-7. Watchdog ...

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Table 10-8. Watchdog Timer Prescale Select, DIV = 5 (CLKwdt = CLK128 / 11) WDP3 WDP2 WDP1 WDP0 ...

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Table 10-9. Watchdog Timer Prescale Select, DIV = 6(CLKwdt = CLK128 / 13) (Continued) WDP3 WDP2 WDP1 WDP0 Table 10-10. Watchdog Timer ...

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Interrupts 11.1 Overview ...

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Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is ...

Page 66

Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled ...

Page 67

I/O-Ports 12.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

Page 68

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...

Page 69

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...

Page 70

Figure 12-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

Page 71

Assembly Code Example C Code Example unsigned char i; Note: 12.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...

Page 72

Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...

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Note: Table 12-2 ure 12-5 in the modules having the alternate function. Table 12-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...

Page 74

Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • OC0A/OC1C/PCINT7, Bit 7 OC0A, ...

Page 75

PDI/MOSI/PCINT2 – Port B, Bit 2 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the AT90USB82/162. MOSI: SPI Master Data output, Slave Data input for SPI channel. When ...

Page 76

MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.. Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV ...

Page 77

Alternate Functions of Port C The Port C alternate function is as follows: Table 12-6. The alternate pin configuration is as follows: • ICP1/INT4/CLK0, Bit 7 ICP1, Input Capture pin 1 :The PC7 pin can act as an input ...

Page 78

Reset, Reset input. External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW, debugWire channel. ...

Page 79

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • HWB/TO/INT7/CTS HWB, Hardware Boot ...

Page 80

TXD1, USART1 Transmit Data : When the USART1 Transmitter is enabled, this pin is config- ured as an ouput regardless of DDRD3. • INT2/AIN1/RXD1 INT2, External Interrupt source 2: The PD2 pin can serve as an external interrupt source to ...

Page 81

Table 12-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...

Page 82

Register Description for I/O-Ports 12.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even ...

Page 83

PORTD – Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 12.4.9 DDRD – Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 12.4.10 PIND – Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial ...

Page 84

External Interrupts 13.1 Overview The External Interrupts are triggered by the INT[7:0] pin or any of the PCINT[12:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT[7:0] or PCINT[12:0] pins are configured as outputs. This ...

Page 85

Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. Table 13-1. ISCn1 Note: 13.2.2 EICRB – External Interrupt Control Register ...

Page 86

EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7:0 – INT[7:0]: External Interrupt Request 7:0 Enable When an INT[7:0] bit is written to one and the I-bit in the Status Register (SREG) is ...

Page 87

Bit 1:0 – PCIF[1:0]: Pin Change Interrupt Flag 1:0 When a logic change on any PCINT[12:8]/[7:0] pin triggers an interrupt request, PCIF1/0 becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), ...

Page 88

Timer/Counter0 and Timer/Counter1 Prescalers 14.1 Overview Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif- ferent prescaler settings. The description below applies to all Timer/Counters used as a general name ...

Page 89

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be ...

Page 90

Bits 6:1 – Res: Reserved These bits are reserved and will always read as zero. • Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will ...

Page 91

Timer/Counter0 with PWM 15.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...

Page 92

The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...

Page 93

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = ...

Page 94

Figure 15-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

Page 95

Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...

Page 96

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x[1: tells the Waveform Generator that no action on the OC0x Register ...

Page 97

Figure 15-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

Page 98

PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 15-6. Fast PWM ...

Page 99

OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[2:0] = ...

Page 100

OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port pin ...

Page 101

Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 mode and PWM mode, where OCR0A is TOP. Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ...

Page 102

Register Description 15.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

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Table 15-4 rect PWM mode. Table 15-4. COM0A1 Note: • Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0] bits ...

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Table 15-4 correct PWM mode. Table 15-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with ...

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TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...

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Table 15-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...

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Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt ...

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Timer/Counter 1 with PWM 16.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear ...

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Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

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See “Output Compare Units” on page Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the ...

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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...

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Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. 7799D–AVR–11/10 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts ...

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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...

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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an input capture unit that can ...

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Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte ...

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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. ...

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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...

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Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...

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PWM refer to page 131. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. ...

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Figure 16-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...

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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit ...

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When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next ...

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OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

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Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is ...

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OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...

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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...

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Figure 16-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 16-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...

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Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A ...

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Table 16-1. COMnA1/COMnB1/ Table 16-2 PWM mode. Table 16-2. COMnA1/COMnB1/ Note: Table 16-3 correct and frequency correct PWM mode. 7799D–AVR–11/10 Compare Output Mode, non-PWM COMnA0/COMnB0/ COMnC1 COMnC0 shows the COMnx[1:0] bit ...

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Table 16-3. COMnA1/COMnB/ Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn[3:2] bits found in the TCCRnB Register, these bits control the count- ing sequence of the counter, the source for maximum (TOP) counter value, and ...

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Table 16-4. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...

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TCCR1B – Timer/Counter1 Control Register B Bit (0x81) Read/Write Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input ...

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If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 16.11.3 TCCR1C – Timer/Counter1 Control ...

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OCR1AH and OCR1AL – Output Compare Register 1 A Bit (0x89) (0x88) Read/Write Initial Value 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B Bit (0x8B) (0x8A) Read/Write Initial Value 16.11.7 OCR1CH and OCR1CL – Output Compare Register ...

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Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector ...

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Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe ...

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SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...

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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...

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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...

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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 7799D–AVR–11/10 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...

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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 17.3 SS Pin ...

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Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...

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Table 17-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 17-3. SPI Transfer Format with CPHA = 0 Figure 17-4. SPI Transfer Format with CPHA = 1 7799D–AVR–11/10 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup ...

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Register Description 17.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...

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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...

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SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...

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USART 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Flow control CTS/RTS signals hardware management • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • ...

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Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

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XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 18-2 Figure 18-2. Clock Generation Logic, Block Diagram Signal description: txclk ...

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Table 18-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 18-1. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = ...

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External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...

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A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...

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USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...

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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...

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For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } ...

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UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit ...

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UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: ...

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Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...

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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...

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Figure 18-5. Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 ...

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Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...

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Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = (Data+Parity Bit Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = ...

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The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave MCU has been addressed, ...

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RTS usage and so associated flow control is enabled using RTSEN bit in UCSRnD. Figure 18-8. shows a reception example. Figure 18-8. Reception Flow Control Waveform Example Figure 18-9. RTS behavior RTS will rise at 2/3 of ...

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Register Description 18.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...

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Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is ...

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Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper- ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating ...

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Receiver will generate a parity value for the incoming data and compare it to the UPMn setting mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 18-5. • Bit 3 – USBSn: Stop Bit Select ...

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UCSRnD – USART Control and Status Register n D Bit Read/Write Initial Value • Bits 1 – CTSEN : USART CTS Enable Set this bit to one by firmware to enable the transmission flow control (CTS). Transmission is allowed ...

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Table 18-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 ...

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Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

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Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

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Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...

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USART in SPI Mode 19.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...

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Table 19-1. Equations for Calculating Baud Rate Register Setting Operating Mode Synchronous Master mode Note: BAUD f OSC UBRRn 19.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, ...

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Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB ...

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Assembly Code Example USART_Init: C Code Example void USART_Init( unsigned int baud ) { } Note: 19.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is ...

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The data written to UDRn is moved from the transmit buf- fer to the shift register when the shift register is ready to send a new frame. Note: The following code examples show a simple ...

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Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) ...

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UCSRnB – USART MSPIM Control and Status Register n B Bit Read/Write Initial Value • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt ...

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UCSRnC – USART MSPIM Control and Status Register n C Bit Read/Write Initial Value • Bit 7:6 - UMSELn[1:0]: USART Mode Select These bits select the mode of operation of the USART as shown in USART Control and Status ...

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However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation ...

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USB Controller 20.1 Features • USB 2.0 Full-speed device • Ping-pong mode (dual bank), with transparent switch • 176 bytes of DPRAM – 1 endpoint of 64 bytes max (default control endpoint) – 2 endpoints of 64 bytes max ...

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USB Module Powering Options Depending on the selected target application power supply (V USB controller requires different powering schemes, see Figure 20-2. Operating modes versus frequency and power-supply 20.3.1 Bus Powered device The following figures show typical implementations for ...

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Figure 20-4. Typical Bus powered application with 3.3V I/O 20.3.2 Self Powered device Figure 20-5. Typical Self powered application with 4.0V to 5.5V I/O. 7799D–AVR–11/10 1µF VBUS UDM UDP UVSS UVCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM D- ...

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Figure 20-6. Typical Self powered application with 3.0V to 3.6 I/O Note: 7799D–AVR–11/10 UVCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM D- Rs=22 UVSS UGND UID UID XTAL1 1. The internal 3.3V regulator is bypassed. Disable the regulator to ...

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Design guidelines The following design guidelines should be met: • Serial resistors on USB Data lines must have 22 Ohms value ( • Traces from the input USB receptacle (or from the cable connection in the case of a ...

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When the USB controller is in reset state: • USBE is not set • the USB controller clock is stopped in order to minimize the power consumption (FRZCLK=1) • the USB controller is disabled • USB is in the suspend ...

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Figure 20-10. USB Endpoint Interrupt vector sources OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 STALLEDI UEINTX.1 TXINI UEINTX.0 Each endpoint has 8 interrupts sources associated with flags, and each source can be enabled to trigger ...

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Freeze clock The firmware has the ability to freeze the clock of USB controller by setting the FRZCLK bit, and thereby reduce the power consumption. When FRZCLK is set still possible to access to the following registers: ...

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Endpoints activation: Endpoint 0 to Endpoint 4 are configured, in the growing order. The memory of each is reserved in the DPRAM. • Endpoint disable: The Endpoint 2 is disabled (EPEN=0), but its memory reservation is internally kept by ...

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SUSPI WAKEUPI PAD status Moreover, the pad can also be put in the Idle mode if the DETACH bit is set. It come back in the Active mode when the DETACH bit is cleared. 20.8 D+/D- Read/write The level of ...

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Be sure to have interrupts enabled (WAKEUPE) to exit sleep mode • Put the MCU in sleep mode Resuming the USB interface • Enable PLL • Wait PLL lock • Clear USB suspend clock • Clear Resume information 20.10 ...

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Table 20-2. • Bit 5:4 – UPDRV[1:0]: USB direct drive values These bits are relevant only when one of the direct drive modes for USB is enable. When UPWE[1:0] is 1:0 the values of these bits are output to ...

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USB Device Operating modes 21.1 Overview The USB device controller supports full speed data transfers. In addition to the default control endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • ...

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Rx and Tx banks are cleared and their internal pointers are restored, • the UEINTX, UESTA0X and UESTA1X are restored to their reset value. The data toggle field remains unchanged. The other registers remain unchanged. The endpoint configuration ...

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Figure 21-2. Endpoint activation flow: As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not acknowledge the packets sent by the host. CFGOK will not be set if the Endpoint size parameter is bigger than ...

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UADD contains the default address 00h after a power- USB reset. ADDEN is cleared by hardware: • after a power-up reset, • when an USB reset is received, • or when the macro is disabled (USBE cleared) When ...

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