ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet - Page 20

• Manufacturer Part Number: ATMEGA16U2-MU
• Description: MCU AVR 16K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Core: AVR8
• Processor Series: ATMEGA16x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Mounting Style: SMD/SMT
• Height: 0.95 mm
• Interface Type: SPI, UART
• Length: 5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 5 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.4.1
7.5
7.5.1
7.5.2
7799D–AVR–11/10
Register Description
General Purpose I/O Registers
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
• Bits 15:12 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 11:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
15
EEAR7
MSB
R/W
R/W
R
X
–
7
0
7
0
14
EEAR6
R/W
R/W
R
–
6
0
X
6
0
13
EEAR5
R/W
R/W
R
–
5
0
X
5
0
12
EEAR4
R/W
R/W
R
X
–
4
0
4
0
11
EEAR11
ATmega8U2/16U2/32U2
EEAR3
R/W
R/W
R/W
X
X
3
3
0
10
EEAR10
EEAR2
R/W
R/W
R/W
2
X
X
2
0
9
EEAR9
EEAR1
R/W
R/W
R/W
1
0
1
X
X
8
EEAR8
EEAR0
LSB
R/W
R/W
R/W
X
X
0
0
0
EEDR
EEARH
EEARL
20