ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet - Page 205
ATMEGA16U2-MU
Manufacturer Part Number
ATMEGA16U2-MU
Description
MCU AVR 16K FLASH USB 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Core
AVR8
Processor Series
ATMEGA16x
Data Bus Width
8 bit
Maximum Clock Frequency
16 MHz
Data Ram Size
1.25 KB
Data Rom Size
512 B
Number Of Programmable I/os
22
Number Of Timers
2
Mounting Style
SMD/SMT
Height
0.95 mm
Interface Type
SPI, UART
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
5 mm
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16U2-MU
Manufacturer:
RALINK
Quantity:
2 400
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21.14 IN endpoint management
21.14.0.1
7799D–AVR–11/10
“Manual” mode
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is
being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
IN packets are sent by the USB device controller, upon an IN request from the host. All the data
can be written by the CPU, which acknowledge or not the bank when it is full.Overview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automatically updated by hardware regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
• after “N” read of UEDATX,
• as soon as RWAL is cleared by hardware.
ATmega8U2/16U2/32U2
205
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