ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet - Page 18

• Manufacturer Part Number: ATMEGA16U2-MU
• Description: MCU AVR 16K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Core: AVR8
• Processor Series: ATMEGA16x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Mounting Style: SMD/SMT
• Height: 0.95 mm
• Interface Type: SPI, UART
• Length: 5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 5 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.2.1
7.3
7799D–AVR–11/10
EEPROM Data Memory
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter-
nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing
modes. The Register File is described in
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
The ATmega8U2/16U2/32U2 contains 512/512/1024 bytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
(512/512/1024 x 8)
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
Compute Address
T1
Memory Access Instruction
“General Purpose Register File” on page
$0000 - $001F
$2FF/$2FF/$4FF (8U2/16U2/32U2)
$0020 - $005F
$0060 - $00FF
$0100
Address valid
CPU
ATmega8U2/16U2/32U2
T2
cycles as described in
Next Instruction
T3
Figure
10.
7-3.
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