ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 142
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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15.3
15.3.1
7766F–AVR–11/10
Counter Unit
Counter Initialization for Asynchronous Mode
The main part of the Timer/Counter4 is the programmable bi-directional counter unit.
3
Figure 15-3. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
asynchronous PLL clock using the Clock Select bits (CS4<3:0>) and the PLL Postscaler for High
Speed Timer bits (PLLTM1:0). When no clock source is selected (CS4<3:0> = 0) the timer is
stopped. However, the TCNT4 value can be accessed by the CPU, regardless of whether clk
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter4 is determined by the setting of the WGM10 and
PWM4x bits located in the Timer/Counter4 Control Registers (TCCR4A, TCCR4C and
TCCR4D). For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
the mode of operation selected by the PWM4x and WGM40 bits. The Overflow Flag can be used
for generating a CPU interrupt.
To change Timer/Counter4 to the asynchronous mode follow the procedure below:
shows a block diagram of the counter and its surroundings.
1. Enable PLL.
2. Wait 100µs for PLL to stabilize .
3. Poll the PLOCK bit until it is set.
4. Configure the PLLTM1:0 bits in the PLLFRQ register to enable the asynchronous mode
(different from 0:0 value).
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNT4
T4
). The timer clock is generated from an synchronous system clock or an
TCNT4 increment or decrement enable.
Select between increment and decrement.
Clear TCNT4 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT4 has reached maximum value.
Signalize that TCNT4 has reached minimum value (zero).
149. The Timer/Counter Overflow Flag (TOV4) is set according to
direction
count
clear
clk
T4
bottom
Control Logic
top
TOV4
ATmega16/32U4
T4
PLLTM1:0
PCK
Timer/Counter4 Count Enable
( From Prescaler )
CK
in the following.
Figure 15-
142
T1
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