ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 39
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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6.10
6.10.1
7766F–AVR–11/10
PLL
Internal PLL
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 6-10.
The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface
and/or High Speed Timer module, the PLL input is supplied from an external low-frequency
clock (the crystal oscillator or external clock input pin from XTAL1).
The internal PLL in ATmega16U4/ATmega32U4 generates a clock frequency between 32MHz
and 96 MHz from nominally 8MHz input.
The source of the 8MHz PLL input clock is the output of the internal PLL clock prescaler that
generates the 8MHz from the clock source multiplexer output (See
face). The PLL prescaler allows a direct connection (8MHz oscillator) or a divide-by-2 stage for a
16MHz clock input.
The PLL output signal enters the PLL Postcaler stage before being distributed to the USB and
High Speed Timer modules. Each of these modules can choose an independent division ratio.
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
ATmega16/32U4
Section 6.10.2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
256
16
32
64
1
2
4
8
for PLL inter-
39
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