ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 183
ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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17.1.4
7766F–AVR–11/10
SPI Status Register – SPSR
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 17-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 17-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 17-4.
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
7
SPIF
R
0
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
Figure 17-3
6
WCOL
R
0
SPR1
0
0
1
1
0
0
1
1
5
–
R
0
and
Leading Edge
Leading Edge
Figure 17-4
Figure 17-3
4
–
R
0
Sample
Rising
Falling
Setup
SPR0
0
1
0
1
0
1
0
1
3
–
R
0
for an example. The CPOL functionality is sum-
and
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
2
–
R
0
Figure 17-4
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
1
–
R
0
ATmega16/32U4
Trailing Edge
Trailing Edge
for an example. The CPOL
Sample
Falling
Rising
Setup
0
SPI2X
R/W
0
SPSR
osc
183
is
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