ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 267
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 267 of 433
- Download datasheet (9Mb)
22.4
22.5
22.6
7766F–AVR–11/10
USB reset
Endpoint selection
Endpoint activation
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as
an answer to the CLEAR_FEATURE USB command.
When an USB reset is detected on the USB line (SE0 state with a minimum duration of 2.5µs),
the next operations are performed by the controller:
If the CPU hardware reset function is activated (RSTCPU bit set in UDCON register), a reset is
generated to the CPU core without disabling the USB controller (that follows the same behavior
than after a standard USB End of Reset, and remains attached). That feature may be used to
enhance device reliability.
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done
by setting the EPNUM2:0 bits (UENUM register) with the endpoint number which will be man-
aged by the CPU.
The CPU can then access to the various endpoint registers and data.
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respected in order to activate an endpoint:
• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.
• all the endpoints are disabled
• the default control endpoint remains configured (see Section 22.3, page 266 for more
details).
ATmega16/32U4
267
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