ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 382
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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Table 29-2.
Notes:
7766F–AVR–11/10
Symbol
t
t
t
t
t
t
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega16U4/ATmega32U4, this parameter is characterized and not 100% tested.
2. Required only for f
3. C
4. f
5. This requirement applies to all ATmega16U4/ATmega32U4 2-wire Serial Interface operation. Other devices connected to the
6. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f
2-wire Serial Bus need only obey the general f
be greater than 6 MHz for the low time requirement to be strictly met at f
time requirement will not be strictly met for f
nected to the bus may communicate at full speed (400 kHz) with other ATmega16U4/ATmega32U4 devices, as well as any
other device with a proper t
Parameter
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
2-wire Serial Bus Requirements (Continued)
Figure 29-3. 2-wire Serial Bus Timing
SCL
> 100 kHz.
SCL
SDA
LOW
t
SU;STA
acceptance margin.
SCL
SCL
t
HD;STA
> 308 kHz when f
t
t
of
requirement.
LOW
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
t
HIGH
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
t
HD;DAT
CK
= 8 MHz. Still, ATmega16U4/ATmega32U4 devices con-
t
LOW
SCL
= 100 kHz.
t
SU;DAT
250
100
Min
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
ATmega16/32U4
SCL
SCL
t
- 2/f
- 2/f
SU;STO
t
CK
CK
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
), thus f
), thus the low
t
CK
BUF
Units
must
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
382
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