ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 341
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
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27.7.10
27.7.11
7766F–AVR–11/10
Reading the Signature Row from Software
Preventing Flash Corruption
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to
High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
Table 27-6.
Note:
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
Bit
Rd
Bit
Rd
Signature Byte
Device Signature Byte 1
Device Signature Byte 2
Device Signature Byte 3
RC Oscillator Calibration Byte
All other addresses are reserved for future use.
Table 27-6 on page 341
7
FHB7
7
–
Signature Row Addressing
Table 28-3 on page 347
6
FHB6
6
–
Table 28-4 on page 348
CC
, the Flash program can be corrupted because the supply voltage is
5
FHB5
5
–
and set the SIGRD and SPMEN bits in SPMCSR. When an
4
FHB4
4
–
for detailed description and mapping of the Extended
Z-Pointer Address
0x0000
0x0002
0x0004
0x0001
3
FHB3
3
–
for detailed description and mapping of the Fuse
2
FHB2
2
EFB2
1
FHB1
1
EFB1
ATmega16/32U4
0
FHB0
0
EFB0
341
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