D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 26

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.6
7.7
Section 8 Data Transfer Controller (DTC)
8.1
8.2
8.3
Rev. 3.00 Sep 15, 2006 page xxiv of xxxiv
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 264
7.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 272
7.5.12 Write Data Buffer Function ................................................................................. 278
7.5.13 DMAC Multi-Channel Operation ........................................................................ 279
7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC,
7.5.15 NMI Interrupts and DMAC.................................................................................. 281
7.5.16 Forced Termination of DMAC Operation............................................................ 282
7.5.17 Clearing Full Address Mode ................................................................................ 283
Interrupts ........................................................................................................................... 284
Usage Notes ...................................................................................................................... 285
Overview........................................................................................................................... 291
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 294
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation........................................................................................................................... 302
8.3.1
8.3.2
8.3.3
8.3.4
Transfer Modes .................................................................................................... 233
Sequential Mode .................................................................................................. 236
Idle Mode............................................................................................................. 239
Repeat Mode ........................................................................................................ 242
Single Address Mode ........................................................................................... 246
Normal Mode ....................................................................................................... 249
Block Transfer Mode ........................................................................................... 252
DMAC Activation Sources .................................................................................. 259
Basic DMAC Bus Cycles..................................................................................... 263
and the DMAC ..................................................................................................... 280
Features................................................................................................................ 291
Block Diagram ..................................................................................................... 292
Register Configuration ......................................................................................... 293
DTC Mode Register A (MRA) ............................................................................ 294
DTC Mode Register B (MRB)............................................................................. 296
DTC Source Address Register (SAR) .................................................................. 297
DTC Destination Address Register (DAR) .......................................................... 297
DTC Transfer Count Register A (CRA)............................................................... 298
DTC Transfer Count Register B (CRB) ............................................................... 298
DTC Enable Registers (DTCER) ......................................................................... 299
DTC Vector Register (DTVECR)........................................................................ 300
Module Stop Control Register (MSTPCR) .......................................................... 301
Overview.............................................................................................................. 302
Activation Sources ............................................................................................... 304
DTC Vector Table ............................................................................................... 305
Location of Register Information in Address Space............................................. 308
................................................................... 291