D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 857

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TIOR3L—Timer I/O Control Register 3L
Bit
Initial value
Read/Write
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
:
:
:
Legend: *: Don’t care
Notes:
TGR3D I/O Control
0
1
IOD3
R/W
7
0
0
1
0
1
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock,
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid
0
1
0
1
0
1
*
this setting is invalid and input capture is not generated.
and input capture/output compare is not generated.
IOD2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR3D
is output
compare
register
TGR3D
is input
capture
register *
IOD1
R/W
5
0
2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
TRG3C I/O Control
Legend: *: Don’t care
Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer
IOD0
R/W
4
0
0
1
0
1
0
1
register, this setting is invalid and input capture/output compare is not
generated.
IOC3
R/W
0
1
0
1
0
1
*
3
0
1 output at compare match
Toggle output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0 output at compare match
Input capture at TCNT4 count-up/
count-down *
0
1
0
1
0
1
0
1
0
1
*
*
TGR3C
is output
compare
register
TGR3C
is input
capture
register
IOC2
R/W
2
0
H'FE83
1
Rev. 3.00 Sep 15, 2006 page 821 of 988
Output disabled
Initial output is
0 output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC3 pin
Capture input
source is channel
4/count clock
IOC1
R/W
1
0
Appendix B Internal I/O Register
IOC0
R/W
0
0
1 output at compare match
Toggle output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0 output at compare match
Input capture at TCNT4 count-up/
count-down
REJ09B0330-0300
TPU3