D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 32

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.2 Register Descriptions ........................................................................................................ 645
15.3 Interface to Bus Master ..................................................................................................... 650
15.4 Operation........................................................................................................................... 651
15.5 Interrupts ........................................................................................................................... 657
15.6 Usage Notes ...................................................................................................................... 657
Section 16 D/A Converter
16.1 Overview........................................................................................................................... 663
16.2 Register Descriptions ........................................................................................................ 666
16.3 Operation........................................................................................................................... 669
Section 17 RAM
17.1 Overview........................................................................................................................... 671
17.2 Register Descriptions ........................................................................................................ 672
17.3 Operation........................................................................................................................... 673
17.4 Usage Note........................................................................................................................ 673
Section 18 ROM (H8S/2351 Only)
18.1 Overview........................................................................................................................... 675
Rev. 3.00 Sep 15, 2006 page xxx of xxxiv
15.1.1 Features................................................................................................................ 641
15.1.2 Block Diagram ..................................................................................................... 642
15.1.3 Pin Configuration................................................................................................. 643
15.1.4 Register Configuration ......................................................................................... 645
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 645
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 646
15.2.3 A/D Control Register (ADCR)............................................................................. 648
15.2.4 Module Stop Control Register (MSTPCR) .......................................................... 649
15.4.1 Single Mode (SCAN = 0)..................................................................................... 651
15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 653
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 655
15.4.4 External Trigger Input Timing ............................................................................. 656
16.1.1 Features................................................................................................................ 663
16.1.2 Block Diagram ..................................................................................................... 664
16.1.3 Pin Configuration................................................................................................. 665
16.1.4 Register Configuration ......................................................................................... 665
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 666
16.2.2 D/A Control Register (DACR)............................................................................. 666
16.2.3 Module Stop Control Register (MSTPCR) .......................................................... 668
17.1.1 Block Diagram ..................................................................................................... 671
17.1.2 Register Configuration ......................................................................................... 672
17.2.1 System Control Register (SYSCR) ...................................................................... 672
.................................................................................................................. 671
................................................................................................. 663
................................................................................ 675