D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 658
D12350F20IV
Manufacturer Part Number
D12350F20IV
Description
IC H8S/2350 MCU 4.5/5.5V 0+K I-T
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12350F20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Quantity
Price
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Section 14 Smart Card Interface
14.3.3
Figure 14.3 shows the Smart Card interface data format. In reception in this mode, a parity check
is carried out on each frame, and if an error is detected an error signal is sent back to the
transmitting end, and retransmission of the data is requested. If an error signal is sampled during
transmission, the same data is retransmitted.
The operation sequence is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start
[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data
Rev. 3.00 Sep 15, 2006 page 622 of 988
REJ09B0330-0300
up resistor.
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
Legend:
Ds
D0 to D7
Dp
DE
When there is no parity error
When a parity error occurs
Data Format
: Start bit
: Data bits
: Parity bit
: Error signal
Ds
Ds
D0
D0
Figure 14.3 Smart Card Interface Data Format
D1
D1
D2
D2
Transmitting station output
Transmitting station output
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Dp
Dp
Receiving station
output
DE
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