D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 748

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 21 Electrical Characteristics
21.3.3
Table 21.6 lists the bus timing.
Table 21.6 Bus Timing
Condition A: V
Condition B: V
Item
Address delay time
Address setup time
Address hold time
Precharge time
CS delay time 1
CS delay time 2
AS delay time
RD delay time 1
RD delay time 2
CAS delay time
Read data setup time
Read data hold time
Read data access
time1
Read data access
time2
Read data access
time3
Rev. 3.00 Sep 15, 2006 page 712 of 988
REJ09B0330-0300
Bus Timing
V
T
V
T
a
a
CC
SS
CC
SS
= –40 to +85°C (wide-range specifications)
= –40 to +85°C (wide-range specifications)
= AV
= AV
= 2.7 to 5.5 V, AV
= 5.0 V ±10%, AV
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AD
AS
AH
PCH
CSD1
CSD2
ASD
RSD1
RSD2
CASD
RDS
RDH
ACC1
ACC2
ACC3
SS
SS
= 0 V, = 2 to 10 MHz, T
= 0 V, = 2 to 20 MHz, T
Min
—
0.5
t
0.5
t
1.5
t
—
—
—
—
—
—
30
0
—
—
—
cyc
cyc
cyc
Condition A
CC
–30
–20
–40
CC
= 2.7 to 5.5 V, V
= 5.0 V ±10%, V
Max
—
—
—
—
—
t
t
t
40
40
40
40
40
40
40
1.0
1.5
2.0
cyc
cyc
cyc
–50
–50
–50
a
a
Min
—
0.5
t
0.5
t
1.5
t
—
—
—
—
—
—
15
0
—
—
—
cyc
cyc
cyc
= –20 to +75°C (regular specifications),
= –20 to +75°C (regular specifications),
Condition B
–15
–10
–20
ref
ref
= 2.7 V to AV
= 4.5 V to AV
Max
20
—
—
—
20
20
20
20
20
20
—
—
1.0
t
1.5
t
2.0
t
cyc
cyc
cyc
–25
–25
–25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
CC
,
,
Test Conditions
Figure 21.8 to
Figure 21.15