D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 322

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 DMA Controller (DMAC)
(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
Module Stop
When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is
entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled.
This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
Medium-Speed Mode
When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-
detected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting
modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt
source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is
Rev. 3.00 Sep 15, 2006 page 286 of 988
REJ09B0330-0300
Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1)
register is read as shown in figure 7.41.
DMA internal
address
DMA register
operation
DMA control
Figure 8.41 Contention between DMAC Register Update and CPU Read
Note: The lower word of MAR is the updated value after the operation in [1].
MAR upper
word read
Idle
CPU longword read
[1]
MAR lower
word read
Transfe
source
Read
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle