D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 265
![IC H8S/2350 MCU 4.5/5.5V 0+K I-T](/photos/28/61/286109/128-bfqfp_sml.jpg)
D12350F20IV
Manufacturer Part Number
D12350F20IV
Description
IC H8S/2350 MCU 4.5/5.5V 0+K I-T
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12350F20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12350F20IV
Manufacturer:
INF
Quantity:
4 834
- Current page: 265 of 1027
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DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR by the DTC.
Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR.
Bit 3
WE1B
0
1
Bit 2
WE1A
0
1
Bit 1
WE0B
0
1
DMAWER
Initial value
R/W
Bit
Description
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are disabled
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are enabled
Description
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
Description
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
:
:
:
:
—
—
7
0
—
—
6
0
—
—
5
0
—
—
4
0
Rev. 3.00 Sep 15, 2006 page 229 of 988
WE1B
R/W
3
0
Section 7 DMA Controller (DMAC)
WE1A
R/W
2
0
WE0B
REJ09B0330-0300
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
WE0A
R/W
0
0
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