HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 163

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.3
3.3.1
The TLB caches address translation table information located in the external memory. The address
translation table stores the physical page number translated from the virtual page number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of logical
addresses and TLB entries.
Entry 31
Entry 0
Entry 1
TLB Functions
Configuration of the TLB
VPN(31−17)
Address array
VPN(11−10)
Figure 3.4 Overall Configuration of the TLB
Ways 0 to 3
ASID(7−0)
V
Section 3 Memory Management Unit (MMU)
Entry 31
Rev.6.00 Mar. 27, 2009 Page 105 of 1036
Entry 0
Entry 1
PPN(31−10) PR(1−0) SZ C D SH
Data array
Ways 0 to 3
REJ09B0254-0600