HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 468

IC SUPERH MPU ROMLESS 240QFP

HD6417727F100C

Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100C

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 410 of 1036
REJ09B0254-0600
Note:
Data is read from memory using the SAR3 value as the data address, and the read
data is stored in the temporary buffer. The read data must be a 32-bit value because it
is used as an address.
Two bus cycles are required if a 16-bit data bus is used to connect to an external
device.
Data is read from the source module using the temporary buffer value as the address,
and the read data is transferred to the data buffer.
The data buffer value is written to the destination module using the DAR3 value as the
destination address.
(When the External Memory Space is Set to 16-bit Width)
The above description uses the memory, transfer source module, or transfer
destination module; in practice, any module can be connected in the addressing
space.
M
M
D
M
C
D
C
D
C
A
A
A
Figure 14.9 Operation in Indirect Address Mode
Temporary
Temporary
Temporary
SAR3
DAR3
SAR3
DAR3
SAR3
DAR3
buffer
buffer
buffer
buffer
buffer
buffer
Data
Data
Data
First and second bus cycles
Third bus cycle
Fourth bus cycle
Transfer source module
Transfer source module
Transfer source module
Transfer destination
Transfer destination
Transfer destination
Memory
Memory
Memory
module
module
module

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