HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 440
![IC SUPERH MPU ROMLESS 240QFP](/photos/28/62/286203/240-bfqfp__prqp0240kc-b_sml.jpg)
HD6417727F100C
Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100C
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 440 of 1098
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Section 14 Direct Memory Access Controller (DMAC)
14.1.3
Table 14.1 shows the DMAC pins.
Table 14.1 Pin Configuration
Channel
0
14.1.4
Table 14.2 summarizes the DMAC registers. DMAC has a total of 18 registers, four registers for
each channel and two registers for controlling all channels.
Table 14.2 DMAC Registers
Channel
0
1
Rev.6.00 Mar. 27, 2009 Page 382 of 1036
REJ09B0254-0600
Pin Configuration
Register Configuration
Name
DMA source address
register 0
DMA destination address
register 0
DMA transfer count
register 0
DMA channel control
register 0
DMA source address
register 1
DMA destination address
register 1
DMA transfer count
register 1
DMA channel control
register 1
Name
DMA transfer request
DREQ acknowledge
DMA request
acknowledge
Abbrevi-
ation
SAR0
DAR0
DMATCR0 R/W
CHCR0
SAR1
DAR1
DMATCR1 R/W
CHCR1
Symbol
DREQ0
DACK0
DRAK0
R/W
R/W
R/W
R/W *
R/W
R/W
R/W *
I/O
Input
Output
Output
1
1
Initial
Value
Undefined
Undefined
Undefined
H'00000000 H'0400002C
Undefined
Undefined
Undefined
H'00000000 H'0400003C
Function
DMA transfer request input from external
device to channel 0
Strobe output to an external I/O at DMA
transfer request from external device to
channel 0
Output showing that DREQ0 has been
accepted
Address
H'04000020
(H'A4000020) *
H'04000024
(H'A4000024) *
H'04000028
(H'A4000028) *
(H'A400002C) *
H'04000030
(H'A4000030) *
H'04000034
(H'A4000034) *
H'04000038
(H'A4000038) *
(H'A400003C) *
4
4
4
4
4
4
4
4
Register
Size
32 bits
32 bits
24 bits
32 bits
32 bits
32 bits
24 bits
32 bits
Access
Size
16, 32 *
16, 32 *
16, 32 *
8, 16, 32 *
16, 32 *
16, 32 *
16, 32 *
8, 16, 32 *
2
2
3
2
2
3
2
2
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