HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 194

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Exception Handling
All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
4.2.4
Table 4.3 lists the exception codes written to bits 11 to 0 of the EXPEVT register (for reset or
general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to
identify each specific exception event. An additional exception register, the TRAPA (TRA)
register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.3
Exception Type
Reset
General exception events
Rev.6.00 Mar. 27, 2009 Page 136 of 1036
REJ09B0254-0600
Exception Codes
Exception Codes
Exception Event
Power-on reset
Manual reset
H-UDI reset
TLB miss/invalid (read)
TLB miss/invalid (write)
TLB miss/invalid/CPU Address error in
repeat loop
Initial page write
TLB protection violation (read)
TLB protection violation (write)
TLB protection violation in repeat loop
CPU Address error (read)
CPU Address error (write)
Unconditional trap (TRAPA instruction)
Illegal general instruction exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Exception Code
H'000
H'020
H'000
H'040
H'060
H'070
H'080
H'0A0
H'0C0
H'0D0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0