HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 810

IC SUPERH MPU ROMLESS 240QFP

HD6417727F100C

Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100C

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 24 USB HOST Module
Register: HcRhPortStatus[1:2]
Bits
31–21
20
19
18
17
Rev.6.00 Mar. 27, 2009 Page 752 of 1036
REJ09B0254-0600
Reset
0h
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Offset: 54–57, 58–5B
Description
Reserved.
PortResetStatusChange (PRSC)
This bit is set when the 10 ms port reset signal has completed.
Writing a 1 clears this bit writing a 0 has no effect.
0 = Port reset is not complete.
1 = Port reset is complete.
PortOverCurrentIndicatorChange (OCIC)
This bit is valid when an over-current condition is reported on
the base of each port. This bit is set when the root hub changes
the PortOverCurrentIndicator bit. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: PortOverCurrentIndicator has not changed. (initial value)
1: PortoverCurrentIndicator has changed.
PortSuspendStatusChange (PSSC)
This bit is set when all resume sequences have completed.
These sequences include 20 ms resume pulse, LS EOP, and 3
ms resychronization delay. Writing a 1 clears this bit. Writing a 0
has no effect. This bit is cleared also when ResetStatusChange
is set.
0: Port resume has not completed. (initial value)
1: Port resume has completed.
PortEnableStatusChange (PESC)
This bit is set when the PortEnableStatus bit is cleared due to a
hardware event. This bit is not set by the change of writing of
HCD. Writing a 1 clears this bit. Writing a 0 has no effect.
0: PortEnableStatus has not changed (initial value)
1: PortEnableStatus has changed

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