HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 333

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.7.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 10.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
10.8
10.8.1
The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is
described below. (The WDT does not run when resets are used for canceling, so keep the RESETP
pin low until the clock stabilizes.)
1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
WTCNT write
WTCSR write
TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count
overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
Address: H'FFFFFF84
Address: H'FFFFFF86
Notes on Register Access
Using the WDT
Canceling Standby Mode
Figure 10.3 Writing to WTCNT and WTCSR
15
15
H'5A
H'A5
Rev.6.00 Mar. 27, 2009 Page 275 of 1036
Section 10 On-Chip Oscillation Circuits
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8
7
7
Write data
Write data
REJ09B0254-0600
0
0