HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 708
HD6417727F100C
Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100C
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
HD6417727F100C
Manufacturer:
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Section 20 Serial IO (SIOF)
(5) A Case of 16 bits Stereo (No.2)
L/R method, rising edge sampling and Lch.transmit data are assigned to slot No. 0, Lch. receive
data are assigned to slot No.1, Lch. receive data are assigned to slot No. 2, Rch. receive data is
assigned to slot No. 3, and frame length is 64 bits.
(6) A Case of 16 bits Stereo (No. 3)
Sync pulse method, falling edge sampling and Lch. data are assigned to slot No. 0, Rch. data is
assigned to slot No. 2, control ch. data 0 is assigned to slot No. 1, control ch. data 0 is assigned to
slot No. 3, and frame length is 128 bits.
Rev.6.00 Mar. 27, 2009 Page 650 of 1036
REJ09B0254-0600
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Setting: TRMD = 00 or 10, REDG = 0,
Setting: TRMD = 11, REDG = 1,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Figure 20.17 Transmit or Receive Timing (16 bits stereo—2)
Figure 20.18 Transmit or Receive Timing (16 bits stereo—3)
TDLE = 1,
RDLE = 1,
CD0E = 0,
Lch. DATA Control ch. 0 Rch. DATA Control ch. 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
Lch. DATA
1 bit delay
Slot No.0
No delay
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0001,
CD0A3 to CD0A0 = 0000,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0001,
Lch. DATA
Slot No.1
1 frame
1 frame
Rch. DATA
Slot No.2
FL = 1101 (frame length 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
FL = 1110 (frame length 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0011,
CD1A3 to CD1A0 = 0000
Rch. DATA
Slot No.3
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0010,
CD1A3 to CD1A0 = 0011
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