HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 277

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.11
Note: * Undefined
BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer
(3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0,
when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not
initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted
every branch.
Bit 31—BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the
branch source address can be calculated. When a branch source address is fetched, this flag is set
to 1. This flag is cleared to 0 in reading BRSR.
Bit 31: SVF
0
1
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0 to
7). These bits indicate the instruction buffer number which stores the last executed instruction
before branch.
Bits 30 to 28:
PID
Even
Odd
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Branch Source Register (BRSR)
BSA
SVF
31
15
15
R
R
0
*
Description
The value of BRSR register is invalid
The value of BRSR register is valid
Description
PID indicates the instruction buffer number.
PiD+2 indicates the instruction buffer number
PID2 PID1 PID0 BSA
BSA
30
14
14
R
R
*
*
BSA
29
13
13
R
R
*
*
BSA
28
12
12
R
R
*
*
BSA
27
27
11
11
R
R
*
*
BSA
BSA
26
26
10
10
R
R
*
*
BSA
BSA
25
25
R
R
9
9
*
*
BSA
BSA
24
24
R
R
8
8
*
*
Rev.6.00 Mar. 27, 2009 Page 219 of 1036
BSA
BSA
23
23
R
R
7
7
*
*
BSA
BSA
22
22
R
R
6
6
*
*
Section 8 User Break Controller
BSA
BSA
21
21
R
R
5
5
*
*
BSA
BSA
20
20
R
R
4
4
*
*
BSA
BSA
19
19
R
R
3
3
*
*
REJ09B0254-0600
BSA
BSA
18
18
R
R
2
*
2
*
BSA
BSA
17
17
R
R
1
1
*
*
BSA
BSA
16
16
R
R
0
*
0
*