HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 649

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear
the TE and RE bits to 0 in the serial control register 2 (SCSCR2), then initialize the SCIF as
follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register 2 (SCTSR2).
Clearing TE and RE to 0, however, does not initialize the serial status register 2 (SCSSR2),
transmit FIFO data register 2 (SCFTDR2), or receive FIFO data register 2 (SCFRDR2), which
retain their previous contents.
Clear TE to 0 after all transmit data are transmitted and the TEND flag in the SCSSR2 is set. The
transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared
to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the SCFTDR2 before TE is
set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Rev.6.00 Mar. 27, 2009 Page 591 of 1036
REJ09B0254-0600