HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 318

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 On-Chip Oscillation Circuits
The clock pulse generator blocks function as follows:
1. PLL Circuit 1
2. PLL Circuit 2
3. Crystal Oscillator
4. Divider 1
5. Divider 2
6. Clock Frequency Control Circuit
7. Standby Control Circuit
8. Frequency Control Register
9. Standby Control Register
Rev.6.00 Mar. 27, 2009 Page 260 of 1036
REJ09B0254-0600
PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock
frequency from the CKIO pin or PLL circuit 2. The multiplication rate is set by the frequency
control register. When this is done, the phase of the leading edge of the internal clock is
controlled so that it will agree with the phase of the leading edge of the CKIO pin.
PLL circuit 2 leaves quadruples the frequency of the crystal oscillator or the input clock
frequency coming from the EXTAL pin. The multiplication ratio is fixed by the clock
operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 10.3
for more information on clock operation modes.
This oscillator is used when a crystal resonator element is connected to the XTAL and EXTAL
pins. It operates according to the clock operating mode setting.
Divider 1 generates a clock at the operating frequency used by the internal clock. The
operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1, as
long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the
frequency control register.
Divider 2 generates a clock at the operating frequency used by the peripheral clock. The
operating frequencies can be 1, 1/2, 1/3,1/4, or 1/6 times the output frequency of PLL Circuit 1
or the clock frequency of the CKIO pin, as long as it stays at or below the clock frequency of
the CKIO pin. The division ratio is set in the frequency control register.
The clock frequency control circuit controls the clock frequency using the MD pin and the
frequency control register.
The standby control circuit controls the state of the clock pulse generator and other modules
during clock switching and sleep/standby modes.
The frequency control register has control bits assigned for the following functions: clock
output/non-output from the CKIO pin, PLL standby, the frequency multiplication ratio of PLL
1, and the frequency division ratio of the internal clock and the peripheral clock.
The standby control register has bits for controlling the power-down modes. See section 9,
Power-Down Modes and Software Reset, for more information.