HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 275
HD6417727F100C
Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100C
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727F100C
Manufacturer:
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Quantity:
10 000
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Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 12:
SCMFDB
0
1
Bit 11—PC Trace Enable (PCTE): Enables PC trace.
Bit 11: PCTE
0
1
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bit 10: PCBA
0
1
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the break condition of channel B.
Bit 7: DBEB
0
1
Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB
0
1
Description
The DMAC cycle condition for channel B does not match
The DMAC cycle condition for channel B matches
Description
Disables PC trace
Enables PC trace
Description
PC break of channel A is set before instruction execution
PC break of channel A is set after instruction execution
Description
No data bus condition is included in the condition of channel B
The data bus condition is included in the condition of channel B
Description
PC break of channel B is set before instruction execution
PC break of channel B is set after instruction execution
Rev.6.00 Mar. 27, 2009 Page 217 of 1036
Section 8 User Break Controller
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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