HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 960

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 PC Card Controller (PCC)
Bit 2—PCC0 Ready Change Enable (P0RE): When the PC card connected to area 6 is on the IC
memory card interface, bit 2 enables or disables the interrupt request when the value of the
RDY/BSY pin is changed. This bit has no meaning on the I/O card interface.
Bit 2: P0RE
0
1
Bit 1—PCC0 Battery Warning Enable (P0BWE): When the PC card connected to area 6 is on
the IC memory card interface, bit 1 enables or disables the interrupt request when the BVD2 and
BVD1 pins are in the state in which “the battery must be changed although the data is guaranteed”.
This bit has no meaning on the I/O card interface.
Bit 1: P0BWE
0
1
Bit 0—PCC0 Battery Dead Enable (P0BDE): When the PC card connected to area 6 is on the
IC memory card interface, bit 0 enables or disables the interrupt request when the BVD2 and
BVD1 pins are in the state in which “the battery must be changed since the data is not
guaranteed”. This bit has no meaning on the I/O card interface.
Bit 0: P0BDE
0
1
Rev.6.00 Mar. 27, 2009 Page 902 of 1036
REJ09B0254-0600
Description
No interrupt occurs for the PC card connected to area 6 regardless of the
value of the RDY/BSY pin
An interrupt occurs for the PC card connected to area 6 when the value of
the RDY/BSY pin is changed from 0 to 1
Description
No interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed although the data is guaranteed” (Initial value)
An interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed although the data is guaranteed”
Description
No interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed since the data is not guaranteed” (Initial value)
An interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed since the data is not guaranteed”
(Initial value)