HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 817

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

24.4.2
MPS in ED, CBP in General TD, and BP0 and OFFSET0 to 7 in Ischoronous TD must be set in
multiples of 4 (4n). In the OpenHCI standard, 1 packet is transferred by ITD in General TD and 1
packet by 1 offset in Ischronous TD. In addition, when the amount of the data specified by TD
during OUT transfer exceeds MAXPACKETSIZE (MPS), a packet transmission is carried out in
MAXPACKETSIZE. Therefore, the setting value can be made as above. This restriction is due to
the difference between the specifications of the HCI interface which is the standard of the IP bus
interface of USB and of the bus interface of SH7727. Data might be correctly written to if data is
transferred from addresses other than 4n address. For example, when a two-byte transfer is carried
out from the address that terminates at 1, a long-word transfer is carried out and an unexpected
data is written to starting address 0.
24.5
24.5.1
When a data packet shorter than MAXPACKETSIZE (short packet) is transferred in the IN data
transfer, following usages are restricted.
1. Usage when a dribble bit is added
2. When receiving the data with final 6 bits in CRC are all 1 (in this case, bit stuffing occurs)
24.5.2
When NAK or STALL is received as a handshake from the USB function module, the following
usage is restricted.
1. Usage where a dribble bit is added
When HUB are connected in multiple steps, a dribble bit may be added at the end of the
packet.
In this case, this USB controller may write IN data in the memory with one byte additionally.
Therefore, usage of 1 is prohibited. In usage of 2, the software must be written to so that no
problem occurs even additional data of 1 byte is written to. In concrete, in the usage to connect
the received short packets are connected in the memory, 1 byte of unnecessary data might be
inserted. Be sure to transfer MAXPACKETSIZE mainly and the processed data will be used so
that the end of the data or head can be recognized when a short packet is sent. In applications
where the receive data size cannot be controlled by software, it is not possible to use software
to remove the 1 byte of unnecessary data. When using the module in such cases, appropriate
countermeasures must be considered.
Restriction on the Memory Access Address
Restrictions on the Data Transfer of USB Controller
Restriction of the Data Size in IN Transfer
Restrictions on the Hub Connection on NAK/STALL Reception
Rev.6.00 Mar. 27, 2009 Page 759 of 1036
Section 24 USB HOST Module
REJ09B0254-0600