UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 113

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UPD78F9200MA-CAC-A

Manufacturer Part Number
UPD78F9200MA-CAC-A
Description
MCU 8BIT 1KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9200MA-CAC-A

Package / Case
*
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
7
Core Processor
78K0S
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
1KB (1K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F9200MA-CAC-A
Manufacturer:
NEC
Quantity:
20 000
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00
count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the
input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at
that timing.
PRM00
CRC00
TMC00
See the description of the respective control registers for details.
ES110
0/1
7
0
7
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ( PD78F920x ONLY)
ES100
0/1
6
0
6
0
Two Capture Registers (with Rising Edge Specified)
(c) 16-bit timer mode control register 00 (TMC00)
(a) Capture/compare control register 00 (CRC00)
ES010
5
0
0
5
0
(b) Prescaler mode register 00 (PRM00)
ES000
4
0
1
4
0
User’s Manual U18172EJ3V0UD
TMC003
3
0
3
0
0
TMC002
CRC002
1
2
0
1
TMC001
CRC001
PRM001
0/1
0/1
1
OVF00
CRC000
PRM000
0/1
1
0
Free-running mode
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000
CR010 used as capture register
Note
.
111

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