UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 333

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

A/D
converter
(
20x only)
Interrupt
functions
Standby
function
μ
Function
PD78F9
A/D conversion
result register
(ADCR,
ADCRH) read
operation
The operating
current at the
conversion
waiting mode
IF0: Interrupt
request flag
registers,
MK0: Interrupt
mask flag
registers
INTM0: External
interrupt mode
register 0
Interrupt
requests are
held pending
Interrupt
request pending
STOP mode
STOP mode,
HALT mode
STOP mode
OSTS:
Oscillation
stabilization
time select
register
(
only)
μ
PD78F920x
Details of
Function
−
When a write operation is performed to the A/D converter mode register (ADM)
and analog input channel specification register (ADS), the contents of ADCR and
ADCRH may become undefined. Read the conversion result following
conversion completion before writing to ADM and ADS. Using a timing other
than the above may cause an incorrect conversion result to be read.
The DC characteristic of the operating current at the STOP mode is not satisfied
at the conversion waiting mode (when A/D converter mode register (ADM) is set
up with bit 7(ADCS) =0 and bit 0 (ADCE) =1) (only comparator consumes
power).
Because P21 and P32 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port
function, an interrupt request flag is set. Therefore, the interrupt mask flag
should be set to 1 before using the output mode.
Be sure to clear bits 0, 1, 6, and 7 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt
mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register,
clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag
(××MK× = 0), which will enable interrupts.
Interrupt requests will be held pending while the interrupt request flag registers
(IF0) or interrupt mask flag registers (MK0) are being accessed.
Multiple interrupts can be acknowledged even for low-priority interrupts.
The LSRSTOP setting is valid only when “Can be stopped by software” is set for
the low-speed internal oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed internal oscillation clock).
The following sequence is recommended for operating current reduction of the
A/D converter in
(ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop
the A/D conversion operation, and then execute the HALT or STOP instruction.
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 11-1).
To set and then release the STOP mode, set the oscillation stabilization time as
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
set by OSTS
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ3V0UD
μ
PD78F920x when the standby function is used: First clear bit 7
Cautions
p. 175
p. 175
pp. 179,
180
p. 181
p. 181
p. 183
p. 184
p. 186
p. 187
p. 187
p. 187
p. 188
p. 188
p. 188
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