UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 225

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)
programmer once again on the already-written device which has been set as "The RESET pin is used as an input-only
port pin (P34)" by the option byte function.
mode.
Be aware of the following when erasing/writing by on-board programming using a dedicated flash memory
Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on.
If the power is supplied to the target system beforehand, it cannot be switched to the flash memory programming
Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to
Remarks 1. ( ): f
LIOCP
1
0
2. If it is selected that low-speed internal oscillator can be stopped by software, supply of
2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator
3. An example of software coding for setting the option bytes is shown below.
4. For details on the timing at which the option byte is referenced, see CHAPTER 12 RESET
to be used.
FUNCTION.
the watchdog timer (WDT) is fixed to low-speed internal oscillation clock.
the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of
bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly,
clock supply is also stopped when a clock other than the low-speed internal oscillation
clock is selected as a count clock to WDT.
While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be
supplied to the 8-bit timer H1 even in the STOP mode.
Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit)
Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit)
OPB CSEG AT 0080H
DB 10010001B
X
= 10 MHz
Figure 15-4. Format of Option Byte ( PD78F950x) (2/2)
CHAPTER 15 OPTION BYTE
User’s Manual U18172EJ3V0UD
; Set to option byte
; Low-speed internal oscillator cannot be stopped
; The RESET pin is used as an input-only port pin (P34).
; Minimum oscillation stabilization time (
Low-speed internal oscillates
2
10
/f
X
)
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