UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 328

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

326
16-bit
timer/
event
counters
00
(
20x only)
Function
μ
PD78F9
PRM00:
Prescaler mode
register 00
Interval timer
External event
counter
Pulse width
measurement
Square-wave
output
PPG output
One-shot pulse
output: software
trigger
One-shot pulse
output: external
trigger
Details of
Function
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a
timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be
used as the input pin (TI010) of the valid edge.
Changing the CR000 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
When reading the external event counter count value, TM00 should be read.
To use two capture registers, set the TI000 and TI010 pins.
The measurable pulse width in this operation example is up to 1 cycle of the timer
counter.
Changing the CR000 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
Changing the CRC0n0 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
The cycle of the pulse generated through PPG output (CR000 setting value + 1)
has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin. Because the external trigger is valid even in this case, the timer is
cleared and started even at the level of the TI000 pin or its alternate-function port
pin, resulting in the output of a pulse at an undesired timing.
Do not set 0000H to the CR000 and CR010 registers.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
Do not input the external trigger again while the one-shot pulse is output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not set the CR000 and CR010 registers to 0000H.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC002 and TMC003 bits.
APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ3V0UD
XP
, and in the latter case the count clock is selected by
Cautions
108, 110,
112
pp. 100,
129
pp. 100,
129
p. 101
pp. 105,
129
pp. 106,
127
pp. 106,
p. 114
p. 116
pp. 117,
129
pp. 117,
129
pp. 119,
125
pp. 119,
125
pp. 120,
126
pp. 121,
124
pp. 121,
126
pp. 122,
126
pp. 123,
124
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