UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 336

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

334
Option
byte
Flash
memory
Function
Low-speed
internal
oscillates
Caution When
the RESET Pin
Is Used as an
Inport-Only Port
Pin (P34)
PG-FP5
programming
GUI setting
value example
Security
settings
Self
programming
function
Details of
Function
If it is selected that low-speed internal oscillator can be stopped by software,
supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless
of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode
register (LSRCM). Similarly, clock supply is also stopped when a clock other than
the low-speed internal oscillation clock is selected as a count clock to WDT.
While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can
be supplied to the 8-bit timer H1 even in the STOP mode.
Be aware of the following when erasing/writing by on-board programming using a
dedicated flash memory programmer once again on the already-written device
which has been set as "The RESET pin is used as an input-only port pin (P34)" by
the option byte function. Before supplying power to the target system, connect a
dedicated flash memory programmer and turn its power on. If the power is
supplied to the target system beforehand, it cannot be switched to the flash
memory programming mode.
The above values are recommended values. Depending on the usage
environment these values may change, so set them after having performed
sufficient evaluations.
After the security setting of the batch erase is set, erasure cannot be performed
for the device. In addition, even if a write command is executed, data different
from that which has already been written to the flash memory cannot be written
because the erase command is disabled.
Self programming processing must be included in the program before performing
self programming.
No instructions can be executed while a self programming command is being
executed. Therefore, clear and restart the watchdog timer counter in advance so
that the watchdog timer does not overflow during self programming. Refer to
Table 16-10 for the time taken for the execution of self programming.
Interrupts that occur during self programming can be acknowledged after self
programming mode ends. To avoid this operation, disable interrupt servicing (by
setting MK0 to FFH, and executing the DI instruction) before a mode is shifted
from the normal mode to the self programming mode with a specific sequence.
RAM is not used while a self programming command is being executed.
If the supply voltage drops or the reset signal is input while the flash memory is
being written or erased, writing/erasing is not guaranteed.
The value of the blank data set during block erasure is FFH.
Set the CPU clock so that it is 1 MHz or more during self programming.
Execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, then execute self programming. At this
time, the HALT instruction is automatically released after 10
clocks (f
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, wait for 8
status, and then execute self programming.
Check FPRERR using a 1-bit memory manipulation instruction.
CPU
APPENDIX D LIST OF CAUTIONS
).
User’s Manual U18172EJ3V0UD
Cautions
μ
s after releasing the HALT
μ
s (MAX.) + 2 CPU
pp. 221,
223
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