UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 152

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

(2) Watchdog timer enable register (WDTE)
150
Address: FF49H
Symbol
WDTE
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH.
Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory
Remarks 1. f
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
7
After reset: 9AH
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
4. When using the flash memory programming by self programming, set the overflow
2. f
3.
4. Figures in parentheses apply to operation at f
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
Figure 8-3. Format of Watchdog Timer Enable Register (WDTE)
RL
X
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and
WDCS3 respectively and the watchdog timer is stopped, then the internal reset
signal does not occur even if the following are executed.
time for the watchdog timer so that enough overflow time is secured (Example 1-
byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.).
signal is generated.
:
: System clock oscillation frequency
: Low-speed internal oscillation clock oscillation frequency
Second write to WDTM
1-bit memory manipulation instruction to WDTE
Writing of a value other than “ACH” to WDTE
6
Don’t care
R/W
5
CHAPTER 8 WATCHDOG TIMER
User’s Manual U18172EJ3V0UD
4
3
RL
= 480 kHz (MAX.), f
2
1
X
= 10 MHz.
0