UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 261

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

16.8.9 Example of internal verify operation in self programming mode
An example of the internal verify operation in self programming mode is explained below.
<1> Set 01H (internal verify 1) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the flash address pointer L (FLAPL) to 00H.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the flash address pointer L compare register (FLAPLC) to FFH.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets flash address pointer L (FLAPL) to the start address.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets flash address pointer L compare register (FLAPLC) to the end address.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
• Internal verify 1
• Internal verify 2
HALT instruction if self programming has been executed.)
Abnormal → <10>
Normal
HALT instruction if self programming has been executed.)
Abnormal → <10>
Normal
→ <11>
→ <11>
CHAPTER 16 FLASH MEMORY
User’s Manual U18172EJ3V0UD
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