SAK-XC866-1FRA AB Infineon Technologies, SAK-XC866-1FRA AB Datasheet - Page 108

• Manufacturer Part Number: SAK-XC866-1FRA AB
• Description: IC MCU 8BIT FLASH 38-TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC866-1FRA AB

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-TSSOP
• Data Bus Width: 8 bit
• Data Ram Size: 750 B
• Interface Type: UART, SSC
• Maximum Clock Frequency: 26.67 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000235420

4.3.3
Table 42
Parameter
Pad operating voltage
On-Chip Oscillator
start-up time
Flash initialization time
RESET hold time
PLL lock-in in time
PLL accumulated jitter
1)
2)
Figure 42
Data Sheet
Flash State
RESET signal has to be active (low) until
PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.
RESET
VDDC
VDDP
OSC
PLL
Pads
t
RST
Power-on Reset and PLL Timing
1)
I)until EVR is stable
Power-on Reset Timing
2)
V
Power-On Reset and PLL Timing (Operating Conditions apply)
PAD
1)
1)Pad state undefined
t
OSCST
V
t
t
t
t
D
Symbol
OSCST
FINIT
RST
LOCK
Reset
PAD
P
II)until PLL is locked
CC
CC –
SR
CC –
CC 2.3
PLL unlock
V
DDC
t
LOCK
–
min. typ.
–
–
2)ENPS control 3)As Programmed
has reached 90% of its maximum value (typ. 2.5V).
Limit Values
104
–
–
160
500
–
–
3)
to Ready-to-Read
III) until Flash go
Initialization
t
max.
–
500
–
–
200
0.7
FINIT
V
ns
µs
µs
µs
ns
Unit Test Conditions
IV) CPU reset is released; Boot
ROM software begin execution
PLL lock
V
(10% – 90%) ≤ 500µs
2)
Electrical Parameters
Ready to Read
DDP
rise time
V1.2, 2007-10
XC866