SAK-XC866-1FRA AB Infineon Technologies, SAK-XC866-1FRA AB Datasheet - Page 34

• Manufacturer Part Number: SAK-XC866-1FRA AB
• Description: IC MCU 8BIT FLASH 38-TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC866-1FRA AB

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-TSSOP
• Data Bus Width: 8 bit
• Data Ram Size: 750 B
• Interface Type: UART, SSC
• Maximum Clock Frequency: 26.67 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000235420

Table 10
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11
Data Sheet
Addr
B1
RMAP = 0, Page 3
80
90
B0
Addr
RMAP = 0
D1
RMAP = 0, Page 0
CA
CB
CC
CD
CE
CF
RMAP = 0, Page 1
CA
CB
CC
CD
CE
CF
D2
D3
RMAP = 0, Page 2
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Name
P3_ALTSEL1
P3 Alternate Select 1 Register
P0_OD
P0 Open Drain Control Register
P1_OD
P1 Open Drain Control Register
P3_OD
P3 Open Drain Control Register
Register Name
ADC_PAGE
Page Register for ADC
ADC_GLOBCTR
Global Control Register
ADC_GLOBSTR
Global Status Register
ADC_PRAR
Priority and Arbitration Register
ADC_LCBR
Limit Check Boundary Register
ADC_INPCR0
Input Class Register 0
ADC_ETRCR
External Trigger Control Register
ADC_CHCTR0
Channel Control Register 0
ADC_CHCTR1
Channel Control Register 1
ADC_CHCTR2
Channel Control Register 2
ADC_CHCTR3
Channel Control Register 3
ADC_CHCTR4
Channel Control Register 4
ADC_CHCTR5
Channel Control Register 5
ADC_CHCTR6
Channel Control Register 6
ADC_CHCTR7
Channel Control Register 7
Port Register Overview (cont’d)
ADC Register Overview
Reset: B7
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 30
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Bit
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
SYNEN
ASEN1 ASEN0
ANON
30
P7
P7
P7
rw
rw
rw
rw
rw
rw
7
7
1
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
OP
w
0
0
r
r
SYNEN
DW
P6
P6
P6
rw
rw
rw
rw
rw
rw
6
6
0
BOUND1
rw
LCC
LCC
LCC
LCC
LCC
LCC
LCC
LCC
P5
P5
P5
P5
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
5
5
0
r
STNR
CTC
rw
w
ETRSEL1
CHNR
ARBM CSM1 PRIO1 CSM0 PRIO0
P4
P4
P4
rw
rw
rw
rw
rw
rh
4
4
Functional Description
STC
rw
P3
P3
P3
rw
rw
rw
rw
3
3
0
0
r
r
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
P2
P2
P2
rw
rw
rw
rw
2
2
0
r
BOUND0
V1.2, 2007-10
rw
ETRSEL0
0
r
PAGE
SAM
PLE
rwh
P1
P1
P1
P1
rw
rw
rw
rw
rw
rw
rh
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
1
1
XC866
rw
rw
rw
rw
rw
rw
rw
rw
BUSY
P0
P0
P0
P0
rw
rw
rw
rw
rw
rh
0
0