SAK-XC866-1FRA AB Infineon Technologies, SAK-XC866-1FRA AB Datasheet - Page 58

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SAK-XC866-1FRA AB

Manufacturer Part Number
SAK-XC866-1FRA AB
Description
IC MCU 8BIT FLASH 38-TSSOP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet

Specifications of SAK-XC866-1FRA AB

Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-TSSOP
Data Bus Width
8 bit
Data Ram Size
750 B
Interface Type
UART, SSC
Maximum Clock Frequency
26.67 MHz
Number Of Programmable I/os
27
Number Of Timers
3
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
SP000235420
3.7
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until V
capacitor at RESET pin. This capacitor value must be selected so that V
0.4 V, but not before V
A typical application example is shown in
V
Typically, the time taken for V
reaches 2.3V. Hence, based on the condition that 10% to 90% V
than 500 µs, the RESET pin should be held low for 500 µs typically. See
Figure 21
Data Sheet
DDC
capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF.
DDC
reaches 0.9*V
Reset Control
Reset Circuitry
100nF
typ.
DDC
DDC
reaches 0.9* V
. The delay of external reset can be realized by an external
DDC
RESET
VSSP
e.g. 300nF
to reach 0.9*V
30k
3.3V/5V
DDC.
54
Figure
VDDP
21. V
VDDC
DDC
EVR
is less than 50 µs once V
220nF
DDP
VSSC
capacitor value is 300 nF.
XC866
Functional Description
DDP
Table
(slew rate) is less
RESET
Figure
V1.2, 2007-10
20) must be
reaches
XC866
22.
DDP

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