SAK-XC866-1FRA AB Infineon Technologies, SAK-XC866-1FRA AB Datasheet - Page 36

• Manufacturer Part Number: SAK-XC866-1FRA AB
• Description: IC MCU 8BIT FLASH 38-TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC866-1FRA AB

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-TSSOP
• Data Bus Width: 8 bit
• Data Ram Size: 750 B
• Interface Type: UART, SSC
• Maximum Clock Frequency: 26.67 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000235420

Table 11
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12
Data Sheet
Addr
CA
CB
CC
CD
CE
CF
D2
D3
RMAP = 0, Page 6
CA
CB
CC
CD
CE
CF
D2
D2
Addr
C0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Name
ADC_CHINFR
Channel Interrupt Flag Register
ADC_CHINCR
Channel Interrupt Clear Register
ADC_CHINSR
Channel Interrupt Set Register
ADC_CHINPR
Channel Interrupt Node Pointer
Register
ADC_EVINFR
Event Interrupt Flag Register
ADC_EVINCR
Event Interrupt Clear Flag Register
ADC_EVINSR
Event Interrupt Set Flag Register
ADC_EVINPR
Event Interrupt Node Pointer Register
ADC_CRCR1
Conversion Request Control Register 1
ADC_CRPR1
Conversion Request Pending
Register 1
ADC_CRMR1
Conversion Request Mode Register 1
ADC_QMR0
Queue Mode Register 0
ADC_QSR0
Queue Status Register 0
ADC_Q0R0
Queue 0 Register 0
ADC_QBUR0
Queue Backup Register 0
ADC_QINR0
Queue Input Register 0
Register Name
T2_T2CON
Timer 2 Control Register
ADC Register Overview (cont’d)
Timer 2 Register Overview
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 20
Reset: 00
Reset: 00
Reset: 00
Reset: 00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Bit
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
CHINC
CHINF
CHINS
CHINP
EVINC
EVINS
EVINP
EVINF
CHP7
EXTR
EXTR
EXTR
32
CH7
CEV
Rsv
Rsv
TF2
rwh
rwh
rwh
rw
rw
rh
rh
rh
rh
7
w
w
w
w
w
w
7
7
7
7
7
7
7
7
7
r
r
CHINC
CHINF
CHINS
CHINP
EVINC
EVINF
EVINS
EVINP
CHP6
TREV FLUSH CLRV TRMD ENTR
LDEV
EXF2
ENSI
ENSI
ENSI
CH6
rwh
rwh
rwh
rw
rw
rh
rh
rh
rh
6
w
w
w
w
w
w
w
6
6
6
6
6
6
6
6
6
0
r
EMPTY
CHINF
CHINC
CHINS
CHINP
EVINC
EVINF
EVINS
EVINP
CHP5
CH5
CLR
PND
rwh
rwh
RF
RF
RF
rw
rw
rh
rh
rh
rh
rh
5
w
w
w
w
w
w
w
5
5
5
5
5
5
5
5
5
0
r
CHINC
CHINS
CHINP
EVINC
CHINF
EVINF
EVINS
EVINP
CHP4
SCAN
CH4
rwh
rwh
EV
rw
rw
rw
rh
rh
rh
rh
rh
4
w
w
w
w
w
4
4
4
4
4
4
4
4
4
V
V
Functional Description
0
r
EXEN2
CHINC
CHINS
CHINP
CHINF
ENSI
rw
rw
rw
rw
rh
3
w
w
3
3
3
3
3
0
0
r
r
0
0
0
0
r
r
r
r
CHINC
CHINS
CHINP
CHINF
ENTR
TR2
rwh
rw
rw
rw
rh
2
w
w
2
2
2
2
2
V1.2, 2007-10
REQCHNR
REQCHNR
REQCHNR
0
0
0
r
r
r
CHINC
CHINF
CHINS
CHINP
EVINC
EVINS
EVINP
EVINF
rw
rw
rh
rh
rh
rh
1
1
w
w
w
w
w
1
1
1
1
1
1
1
1
0
r
XC866
ENGT
ENGT
rw
rw
CHINC
CHINF
CHINS
CHINP
EVINC
EVINS
EVINP
EVINF
RL2
CP/
rw
rw
rw
rh
rh
0
0
w
w
w
w
0
0
0
0
0
0
0
0