UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 103

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

FFECH to
FFEFH
FFA7H
FFA8H
FFA9H
FFAAH
FFABH
FFACH
FFADH
FFAEH
FFAFH
to FFB9H
FFBAH
FFBBH
FFBCH
FFBDH
FFBEH
FFBFH
FFC0H to
FFDFH
FFE0H
FFE1H
FFE2H
FFE3H
FFE4H
FFE5H
FFE6H
FFE7H
FFE8H
FFE9H
FFEAH
FFEBH
FFF0H
FFF1H to
FFFAH
FFFBH
Address
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1. The reset value of RESF varies depending on the reset source.
Remark
IICACTL0
IICACTL1
IICAF0
IICAS0
IF0
IF1
MK0
MK1
PR0
PR1
RESF
IICWL
IICWH
TMC00
PRM00
CRC00
TOC00
LVIM
LVIS
IMS
PCC
Symbol
2. The reset values of LVIM vary depending on the reset source and setting of option byte.
3. The reset values of LVIS vary depending on the reset source.
4. Reset signal generation makes the setting of the ROM area undefined.
−
−
−
−
−
IF0L
IF0H
IF1L
IF1H
MK0L
MK0H
MK1L
MK1H
PR0L
PR0H
PR1L
PR1H
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
corresponding to each product as indicated in Table 3-1 after release of reset.
<MSTS0> <ALD0> <EXC0> <COI0> <TRC0> <ACKD0> <STD0> <SPD0>
<TMIF010> <TMIF000>
<TMMK010> <TMMK000>
<WUP>
<LVION>
<TMPR010> <TMPR000>
<IICE0> <LREL0> <WREL0> <SPIE0> <WTIM0> <ACKE0> <STT0> <SPT0>
<STCF> <IICBSY>
<SREIF6>
<SREMK6>
<SREMK6>
ES110 ES100 ES010
RAM2
Table 3-7. Special Function Register List: 78K0/KA2-L (20-pin products) (4/4)
7
−
0
−
−
−
0
0
0
0
−
0
0
1
1
1
1
−
−
0
<OSPT00> <OSPE00> TOC004
RAM1
6
0
−
−
0
0
0
0
−
0
0
0
1
−
−
0
0
−
−
1
1
1
1
1
<CLD0> <DAD0> <SMC0> <DFC0>
RAM0
−
−
−
−
−
5
0
0
−
−
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
<PMK3> <PMK2> <PMK1> <PMK0> <LVIMK>
WDTRF
<PIF3> <PIF2> <PIF1> <PIF0> <LVIIF>
<PPR3> <PPR2> <PPR1> <PPR0> <LVIPR>
ES000
4
0
−
−
−
−
0
0
0
0
−
0
0
0
1
1
1
1
1
1
−
0
−
0
Bit No.
<TMIF51>
<TMPR51>
<LVS00> <LVR00>
<TMIFH1>
<TMMK51>
TMC003 TMC002 TMC001 <OVF00>
<TMMKH1>
<TMPRH1>
ROM3
LVIS3
3
0
−
0
−
0
0
0
−
0
−
−
0
−
−
1
1
CRC002 CRC001 CRC000
ROM2
LVIS2
PCC2
2
0
−
0
−
−
−
0
0
−
0
0
0
1
1
1
1
1
1
−
−
<STCEN>
<STPR6> <SRPR6>
<LVIMD> <LVIF>
<STIF6> <SRIF6>
PRM001 PRM000
<STMK6> <SRMK6>
TOC001
ROM1
LVIS1
PCC1
1
0
−
0
−
−
−
−
0
0
1
1
−
−
1
1
<ADMK>
<TOE00>
<IICAIF0>
<IICAMK0>
<IICAPR0>
<ADIF>
<IICRSV>
<ADPR>
LVIRF
ROM0
LVIS0
PCC0
−
−
−
−
−
0
0
−
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
−
−
−
−
−
CHAPTER 3 CPU ARCHITECTURE
1
√
√
√
√
−
−
−
−
−
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
Simultaneously
Number of Bits
Manipulated
√
√
√
√
−
√
√
√
−
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
8
√
Therefore, set the value
16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
−
−
−
−
CFH
00H
00H
00H
Reset
After
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
01H
00H
00H
−
−
−
−
−
Note1
Note2
Note3
Note4
492
501
499
497
664
503
503
248
253
249
251
672
675
598
598
598
598
606
606
606
606
613
613
613
613
699
204
−
−
−
−
−
89