UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 743

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjustment
Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
ADDW
SUBW
CMPW
MULU
DIVUW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
ROR4
ROL4
ADJBA
ADJBS
MOV1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
register (PCC).
AX, #word
AX, #word
AX, #word
X
C
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
[HL]
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Operands
Bytes
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
2
2
2
3
3
2
3
2
3
3
2
3
2
Note 1
16
25
10
10
6
6
6
2
4
2
4
4
4
2
2
2
2
4
4
6
−
4
−
6
6
−
4
−
6
Clocks
Note 2
12
12
−
−
−
−
−
−
6
−
6
−
−
−
−
−
−
−
−
7
7
−
7
7
8
8
−
8
8
(saddr.bit) ← CY
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
AX ← A × X
AX (Quotient), C (Remainder) ← AX ÷ C
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
(saddr) ← (saddr) − 1
rp ← rp + 1
rp ← rp − 1
(CY, A
(CY, A
(CY ← A
(CY ← A
A
(HL)
A
(HL)
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
CY ← (saddr.bit)
CY ← sfr.bit
CY ← A.bit
CY ← PSW.bit
CY ← (HL).bit
sfr.bit ← CY
A.bit ← CY
PSW.bit ← CY
(HL).bit ← CY
3 − 0
3 − 0
3 − 0
7 − 4
← (HL)
← (HL)
7
0
← A
← A
← (HL)
← (HL)
0
7
, A
, A
CPU
0
7
7
0
3 − 0
7 − 4
, A
, A
← CY, A
← CY, A
) selected by the processor clock control
CHAPTER 27 INSTRUCTION SET
7 − 4
3 − 0
, (HL)
, (HL)
m − 1
m + 1
Operation
← A
← A
3 − 0
7 − 4
m − 1
m + 1
m
m
← A
← A
) × 1 time
) × 1 time
← A
← A
3 − 0
3 − 0
m
m
) × 1 time
) × 1 time
,
,
Z AC CY
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
729