UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 507

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Address: FFA7H
IICACTL0
Symbol
Notes 1. The IICAS0 register, the STCF and IICBSY bits of the IICAF0 register, and the CLD0 and DAD0
Caution If the operation of I
Be sure to set this bit (1) while the SCLA0 and SDLA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• Reset
WREL0
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 =
1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
LREL0
IICE0
IICE0
<7>
0
1
0
1
0
1
Note s 2, 3
Note s 2, 3
2. The signals of these bits are invalid while the IICE0 bit is 0.
3. When the LREL0 and WREL0 bits are read, 0 is always read.
After reset: 00H
is low level, and the digital filter is turned on (DFC0 of the IICACTL1 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of I
(IICE0 = 1).
bits of the IICACTL1 register are reset.
Stop operation. Reset the IICA status register 0 (IICAS0)
Enable operation.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICACTL0) and IICA status register 0 (IICAS0) are cleared
to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
LREL0
<6>
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (1/4)
WREL0
<5>
R/W
2
C is enabled (IICE0 = 1) when the SCLA0 line is high level, the SDAA0 line
SPIE0
<4>
WTIM0
Exit from communications
<3>
I
2
C operation enable
Wait cancellation
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Condition for setting (WREL0 = 1)
• Set by instruction
ACKE0
<2>
CHAPTER 15 SERIAL INTERFACE IICA
Note 1
. Stop internal operation.
STT0
<1>
SPT0
<0>
493
2
C