UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 418

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(8) Successive approximation register (SAR)
(9) 10-bit A/D conversion result register (ADCR)
(10) 8-bit A/D conversion result register L (ADCRL)
(11) 8-bit A/D conversion result register H (ADCRH)
(12) Controller
(13) AV
(14) AV
(15) V
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The SAR register is a 10-bit register that sets a result compared by the A/D voltage comparator, 1 bit at a time starting
from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR, ADCRH).
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its lower 10 bits (the higher 6 bits
are fixed to 0).
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRL register stores the lower 8 bits of the A/D conversion result.
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
Caution When data is read from ADCR, ADCRL, and ADCRH, a wait cycle is generated. Do not read data
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When all the specified A/D conversion has been completed, this
controller generates an A/D conversion end interrupt request signal (INTAD).
This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the V
pin when port 2 is used as a digital port.
The signal input to ANI0 to ANI10 is converted into a digital signal, based on the voltage applied across AV
AV
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the V
even when the A/D converter is not used.
This is the ground potential pin. In the 78K0/KY2-L and 78K0/KA2-L, V
of the A/D converter. Be sure to connect V
SS
SS
REF
SS
pin
.
pin (78K0/KB2-L and 78K0/KC2-L only)
pin
from ADCR, ADCRL, and ADCRH when the peripheral hardware clock (f
refer to CHAPTER 31 CAUTIONS FOR WAIT.
SS
to a stabilized GND (= 0 V).
SS
functions alternately as the ground potential
CHAPTER 12 A/D CONVERTER
PRS
) is stopped. For details,
REF
SS
and
404
pin
DD