UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 511

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(2) IICA status register 0 (IICAS0)
Address: FFAAH
Symbol
IICAS0
This register indicates the status of I
This register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Caution Reading the IICAS0 register while the address match wakeup function is enabled (WUP = 1) in
Remark
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
Remark
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
• Reset
Condition for clearing (ALD0 = 0)
• Automatically cleared after the IICAS0 register is
• When the IICE0 bit changes from 1 to 0 (operation
• Reset
STOP mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup operation is
stopped), regardless of the INTIICA0 interrupt request, the change in status is not reflected until
the next start condition or stop condition is detected. To use the wakeup function, therefore,
enable (SPIE0 = 1) the interrupt generated by detecting a stop condition and read the IICAS0
register after the interrupt has been detected.
STT0:
WUP:
MSTS0
MSTS0
read
stop)
stop)
ALD0
<7>
0
1
0
1
Note
than the ALD0 bit of the IICAS0 register. Therefore, when using the ALD0 bit, read the data of this
bit before the data of the other bits.
LREL0:
IICE0:
Bit 1 of IICA control register 0 (IICACTL0)
Bit 7 of IICA control register 1 (IICACTL1)
After reset: 00H
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. The MSTS0 bit is cleared.
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (1/3)
ALD0
<6>
Bit 6 of IICA control register 0 (IICACTL0)
Bit 7 of IICA control register 0 (IICACTL0)
EXC0
<5>
2
C.
R
COI0
<4>
Detection of arbitration loss
TRC0
<3>
Master status
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a “loss”.
ACKD0
CHAPTER 15 SERIAL INTERFACE IICA
<2>
STD0
<1>
SPD0
<0>
497